|
Design of a High Gain Low Noise Amplifier at 3.3 GHz using CMOS Technology |
|---|---|
| รหัสดีโอไอ | |
| Creator | Ravi Kumar Kandagatla |
| Title | Design of a High Gain Low Noise Amplifier at 3.3 GHz using CMOS Technology |
| Contributor | Surya Teja K, Ramya S, Vijaya Kumar P, Dileep Kumar P |
| Publisher | Faculty of Engineering Mahasasakham University |
| Publication Year | 2568 |
| Journal Title | Engineering Access |
| Journal Vol. | 11 |
| Journal No. | 1 |
| Page no. | 45-49 |
| Keyword | Low noise amplifier, CMOS, 5G Communication, Inductor, Image Rejection |
| URL Website | https://ph02.tci-thaijo.org/index.php/mijet/index |
| Website title | THAIJO Engineering Access |
| ISSN | 2730-4175 |
| Abstract | Low noise amplifier (LNA) is the important device used in field of communication. The main objective of this device is to boost the level of low power signal to a sufficient level without altering the signal to noise ratio in the circuit. This paper proposes a novel LNA with improved gain and optimized noise figure using Gain Enhancement and Image Rejection (GEIR) technique. CMOS technology is used in proposed work. LNA using CMOS at 90 nm technology is proposed using image rejection. The proposed amplifier boosts signal amplification using a 4 transistor CMOS GEIR network by providing proper input and output impedance matching. Simulations are performed using Cadence tool. The proposed amplifier is operating at a center frequency of 3.3 GHz and is able to achieve 14.5 dB gain and low noise figure. This could be useful in WIMAX application where high speed data rate at wide area coverage is required. |
