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Design of power efficient, high-speed 4-bit comparator in UMC 180 nm technology |
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| รหัสดีโอไอ | |
| Creator | 1. Sudheer Raja Venishetty 2. Anil Kumar Chidra |
| Title | Design of power efficient, high-speed 4-bit comparator in UMC 180 nm technology |
| Publisher | Faculty of Engineering, Khon Kaen University |
| Publication Year | 2564 |
| Journal Title | Engineering and Applied Science Research |
| Journal Vol. | 48 |
| Journal No. | 1 |
| Page no. | 40-47 |
| Keyword | Power, Comparator, Performance metrics, Gate diffusion input logic |
| URL Website | https://www.tci-thaijo.org/index.php/easr/index |
| Website title | Engineering and Applied Science Research |
| ISSN | 2539-6161 |
| Abstract | Power, Area, and Delay are the three important performance metrics used for analyzing any digital circuit. This paper explores different digital circuit design styles to achieve a better trade-off between the performance metrics. 4-bit Comparator based on 2's complement addition principle is designed and implemented using these different digital circuit principles. Full adder and the other components required to implement 4-bit comparator are designed and implemented using Majority Gate Logic (MGL), Mirror Adder Logic (MAL), Complementary Pass Transistor Logic (CPL), Transmission Gate Logic (TGL) and Gate Diffusion Input Logic (GDI) for studying their performance under different stringent conditions of Temperature, Power supply, etc. The circuits are realized in the UMC 180 nm process using the Cadence Spectre Simulator with a power supply of 1.8 V. |
